Robuspic - Robust Mixed-Signal Design-Methodologies for Smart Power ICs

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Publications

Publications resulted from the ROBUSPIC project is given here. Some of the presentations are also available.

1.	H. Taher, D. Schreurs and B. Nauwelaers, "Black Box Modelling of LDMOSFET", Proc. 12th URSI Forum, Palace of the Academies, Brussels, Belgium, p. 61, 10 December 2004
2.	E. Napoli, V. Pathirana, F. Udrea, G. Bonnet, T. Trajkovic, G. Amaratunga. A compact model for thin SOI LIGBTs: description, experimental verification and system application. Proceedings of ISPSD '05. May 23-26, Pages:95-98, 2005 [presentation]
3.	E. Napoli , V. Pathirana, F. Udrea. Accurate Physical Model for the Lateral IGBT in Silicon On Insulator Technology. ISIE 2005, June 20-23, Durovnik, Croatia, 2005 [presentation]
4.	C. Anghel, Y. S. Chauhan, N. Hefyene, A. M. Ionescu. A Physical Analysis of HV MOSFET Capacitance Behaviour. ISIE 2005, June 20-23, Durovnik, Croatia, 2005
5.	R. Gillon. Aspects of Robust Mixed-Signal Design in Smart-Power IC Processes. ISIE 2005, June 20-23, Durovnik, Croatia, 2005 [presentation]
6.	E. Napoli, V. Pathirana, F. Udrea. Modeling Turn-off Voltage rise in SOI LIGBT. 15th Workshop on Modelling and Simlulation of Electron devices. MSED'05, 4-5 July, Pisa, Italy, 2005
7.	E. Napoli, V. Pathirana, F. Udrea. Modeling Turn-off Voltage rise in SOI LIGBT. Journal of Computation Electronics. Special issue on MSED'05 workshop. MSED'05 4-5 July, Pisa, Italy, 2005
8.	S. Gamage, V. Pathirana and F. Udrea. A compact steady-state self-heating model for a thin SOI LIGBT. IEEE CAS2005 conference, Sinaia, Romania, October, 2005
9.	E. Napoli, V. Pathirana, F. Udrea. Modeling Voltage Derivative During Inductive Turnoff in Thin SOI LIGBT. IEEE Trans. on Electron devices, Vol. 52, No. 12, pp. 2776-2783, 2005
10.	V.Pathirana, E. Napoli, S. Gamage, F. Udrea. A Complete Analytical Model for the Lateral Insulated Gate Bipolar Transistor on SOI technology. , IEEE Tencon 2005 conference, Melbourne, Australia, November, 2005
11.	Y. S. Chauhan, C. Anghel, F. Krummenacher, R. Gillon, A. Baguenier, B. Desoete, S. Frere, A. M. Ionescu and M. Declercq, "A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor". Accepted at ISQED, March 2006
12.	E. Napoli and F. Udrea, Circuital implementation of deep depletion SOI power devices, accepted for oral presentation at SPEEDAM 2006 , Taormina, Italy, May 2006
13.	H.Taher, D. Schreurs and B. Nauwelaers, "Black Box Modelling at the Circuit level: Op-Amp as a Case Study ", in/ Proc. The 13th IEEE Mediterranean Electrotechnical Conference, /Benalmádena (Málaga), Spain, May 16-19, 2006
14.	D. Schreurs, M. Myslinski and H. Taher, "Large-Signal Behavioural Modelling - From Transistor to Amplifier", IET (IEE) TARGET Workshop in Cambridge, "High Efficiency Power Amplifier Design for Next Generation Wireless Applications", Cambridge University, UK, 23 May 2006
15.	D. Schreurs, H. Taher, M. Myslinski, K. Remley and B. Nauwelaers, "Modeling of Memory Effects from Large-Signal Measurements", IEEE International Microwave Symposium Workshop on “Memory Effects in Power Amplifiers”, 11 June 2006
16.	S. Gamage, V. Pathirana, Z. Ali and F. Udrea. A fully coupled compact self-heating model for a thin SOI LIGBT with packaging., In proceedings of IEEE ESTC2006 conference, Dresden, Germany, September, 2006
17.	Y. S. Chauhan, C. Anghel, F. Krummenacher, A. M. Ionescu, M. Declercq, R. Gillon, S. Frere, B. Desoete, and C. Maier, "A Highly Scalable High Voltage MOSFET Model", IEEE European Solid-State Device Research Conference (ESSDERC), Montreux, Switzerland, Sept. 2006
18.	A. S. Roy, Y. S. Chauhan, J.-M. Sallesse, C. C. Enz, A. M. Ionescu, and M. Declercq, "Partitioning Schemes in the Lateral Asymmetric MOSFET", IEEE European Solid-State Device Research Conference (ESSDERC), Montreux, Switzerland, Sept. 2006
19.	S. Gamage, V. Pathirana and F. Udrea. A dynamic self heating model for power SOI Lateral Insulated Gate Bipolar Transistors., in Proceedings of the IEEE international SOI conference, pp 99-100, 2006
20.	S. Gamage, V. Pathirana and F. Udrea. Fully coupled dynamic self-heating model for power SOI Lateral Insulated Gate Bipolar Transistors., in Proceedings of the 2006 Bipolar/BiCMOS Circuit and Technology Meeting, pp. 287–290, 2006
21.	Sahan S. H. U. Gamage, Vasantha Pathirana and Florin Udrea, Electro-Thermal Model for a SOI-based LIGBT. IEEE Transactions on Electron Devices, vol. 53 , no. 7, pp. 1689–1704, 2006
22.	C. Anghel, B. Bakeroot, Y. S. Chauhan, R. Gillon, C. Maier, P. Moens, J. Doutreloigne, and A. M. onescu, "New Method for Threshold Voltage Extraction of High Voltage MOSFETs based on Gate-to-Drain Capacitance Measurement", accepted at IEEE Electron Device Letters, 2006
23.	V. Pathirana, E. Napoli., F. Udrea and S. Gamage, An Analytical Model for the Lateral Insulated-Gate Bipolar Transistor (LIGBT) on Thin SOI, IEEE Transactions on Power Electronics, vol 21, No. 6, November, pp. 1521-1528, 2006
24.	Y. S. Chauhan, C. Anghel, F. Krummenacher, C. Maier, R. Gillon, B. Bakeroot, B. Desoete, S. Frere, A. Baguenier Desormeaux, A. Sharma, M. Declercq, and A. M. Ionescu,"Scalable General High Voltage MOSFET Model inlcuding Quasi-Saturation and Self-Heating effect", article in press at Solid State Electronics, 2006
25.	Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "Analysis and Modeling of Lateral Non-Uniform Doping in High-Voltage MOSFETs", accepted at IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 2006
26.	A. S. Roy, Y. S. Chauhan, C. C. Enz, J.-M. Sallesse, "Noise Modeling in Lateral Asymmetric MOSFET", accepted at IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 2006
27.	Y. S. Chauhan, F. Krummenacher, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling", accepted at IEEE International Conference on VLSI Design, Banglore, India, Jan. 2007
28.	Y. S. Chauhan, F. Krummenacher, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "Compact Modeling of Lateral Non-uniform Doping in High-Voltage MOSFETs", accepted in IEEE Transactions on Electron Devices (TED)
29.	W. Grabinski, T. Grasser, G. Gildenblat, G. Smit, M. Bucher, A. C. T. Aarts, A. Tajic, Y. S. Chauhan, A. Napieralski, T. A. Fjeldly, B. Iniguez, G. Iannaccone, M. Kayal, W. Posch, G. Wachutka, F. Pregaldiny, C. Lallement, L. Lemaitre, "MOS-AK: Open Compact Modeling Forum", (invited) International Workshop on Compact Modeling (IWCM), Yokohama, Japan, Jan. 2007

Smarter Power

Silvaco results 2D simulation
(Current density in a MOSFET)

SABER software
(example of circuit implementation)

Experimental characteristics
(IGBT Turn off)

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