Project Objectives

Smart-Power IC’s are gathering momentum as the technology of choice for achieving unprecedented power-efficiency and rational energy-usage in consumer appliances and equipment for the industrial, automotive or housing markets. These IC’s present many technical challenges both in their design and manufacturing. Indeed, to be ‘Smart’, these IC’s make use of logic, micro-processors and memory, which only advanced submicron IC-fabrication processes can offer at a reasonable cost. However, for every new process generation, improvements of the gate-density in digital circuits come along with a reduction in the maximum voltage ratings for the core transistors. On the other hand, the power-handling capability of Smart-Power IC’s involves withstanding voltages up to several hundreds Volts and carrying up to a few tens of Amperes in harsh environments with adverse temperature conditions, voltage surges and sudden discharges. These conflicting requirements must be addressed during the development of Smart-power IC’s, by enhancing the process-platform with high-voltage or power devices, and by adopting specific design practices.

The purpose of this project is to support these specific Smart-Power design practices with adequate tools and methods that are not available today in industrial design-flows. The project is focussing especially on new simulation tools that will promote the robustness of mixed-signal power IC’s: Robustness against harsh environments, which is key for the functionality of Smart-Power IC’s, but also robustness against process variations and device degradations which mainly have an impact on the cost. One should notice that in the field of Smart-Power IC’s both aspects are equally important, as the IC’s are included in appliances which are already available on consumer markets where the pressure on costs is huge. In order to properly assess the impact of the new methodologies, they will be implemented in industrial design-flows and demonstrated on several test-cases.

There are two sides to robustness : external robustness that deals with perturbations emanating from the environment and internal aspects of which process variations and transistor aging are typical examples.

Innovation

• Highly accurate, EKV based, compact electro-thermal models for L- and V-DMOS devices.
• Highly accurate, compact electro-thermal models for LIGBT devices.
• Exploration of the use of these DMOS and LIGBT models for devices built on SOI substrates.
• Enhanced physical insight in the degradation of DMOS and LIGBT devices due to hot carrier injection.
• Extended DMOS and LIGBT model accounting for the hot-carrier induced parameter shift and demonstrated methodology to apply it in the design flow.
• Condition monitoring circuit to determine DMOS ageing on-circuit.
• Implement process variations in the DMOS and LIGBT models.
• Extend DMOS and LIGBT model for large area, parallel closed-cell structures.
• Specific model for DMOS matching.
• Highly accurate electro-thermal simulation including package.
• Chip level EMC simulations.
• Comparison of state-space black models with transistor level simulations for system level optimisation; identification of the preferred method.
• Integration of all models in industrial design flows for smart power circuits
• Demonstration of improvement in robustness for smart power circuits designed through the new flow and models